Box of
You AMD relics
Xeon ruled So did dinosaurs
Ибраги́м
Xeon ruled So did dinosaurs
Athlon was special, so was Coal
Mark
Intel ME*
ikr, i'm just lazy =)
Ибраги́м
ikr, i'm just lazy =)
I know u just lazy. Every enemy of Intel is.
Box of
Athlon was special, so was Coal
Don't trust a relic Be Epyc
Ибраги́м
Don't trust a relic Be Epyc
Let me show you what we do best: power abuse
Ludovic 'Archivist'
Mocking Intel will get you banned sire
He is not so wrong but the preferred way to say it is "ultra energy efficient"
Ибраги́м
Box of
9900K
28 cores @ 5 GHz
Ludovic 'Archivist'
I know. They also have Y
Which counter intuitively doesn't mean "why is it so slow"
Box of
Even industrial cooler can't keep up
Ибраги́м
28 cores @ 5 GHz
Wrong. It's 8 cores
Ludovic 'Archivist'
Even industrial cooler can't keep up
Propane evaporation cooling
Ludovic 'Archivist'
Nothing is impossible to cool with enough gas
Box of
Wrong. It's 8 cores
Oh, so in Intel camp you don't talk about that?
Ибраги́м
28 cores @ 5 GHz
Oh u mean our glorious demo
Box of
Yes
Box of
Then AMD came with 32 core air cooled threadripper
Ludovic 'Archivist'
Then AMD came with 32 core air cooled threadripper
Not really, they came with a pair of two CPU with 16 core they fitted in one socket
Ludovic 'Archivist'
And split memory bandwidth between them
Ludovic 'Archivist'
Magic glue
And the shadow of NUMA latency
Box of
Intel can wish to have something like that
Box of
And the shadow of NUMA latency
Not much of a problem if software isn't garbage
Ludovic 'Archivist'
Even if AMD amortissised the cost
Ludovic 'Archivist'
It is
Box of
Considering Intel's current problems it isn't
Box of
It's the only way if you want to push big core counts
Ludovic 'Archivist'
It means CPU1 interrupts to CPU0 stop the process that is done there, do memory operations that may issue cache misses (no hyperthreading) before resuming
Ludovic 'Archivist'
Infinity Fabric
I know, but it allows just slurping from L3 for free
Ludovic 'Archivist'
So partial loading and RAM latency happen
Anonymous
Hello friends I have a doubt What is %2d in c language
Anonymous
two int
Anonymous
two int
Means?
Ludovic 'Archivist'
Infinity Fabric
So if each CPU run a different application (web server/database) (video game/streaming encoder) the memory access is completely non uniform
Anonymous
The width is two
Box of
You can either make software that's aware of that or stick to 4 core designs for next decade
Ибраги́м
That's where industry is going
Which Industry? The flour?
Ибраги́м
Anonymous
Means?
The width of the number is two
Ludovic 'Archivist'
Or AMD just keep lowering latency till it's negligible
They could add a L3 cache management coprocessor and that was originally an idea they had iirc
Box of
Ludovic 'Archivist'
They might do it now as there are rumours of adding more CCXs
They can, it will save me lots of pain devising memory access over 4 Epyc processors in the same motherboard
Ludovic 'Archivist'
Particularly when what I code is very sensitive to this
Ludovic 'Archivist'
Well, AMD CPUs would be cool if they had cache prefetch instructions that worked
Anonymous
learn
Box of
learn
Cool idea. Wanted to do it today but it didn't exactly work so I hope to do it tomorrow
Anonymous
my English is very poor,😕️
Ludovic 'Archivist'
The poor English of the majority makes England rich
Anonymous
Tq Rose
Anonymous
#cppbook
Anonymous
Send of c also bro
Anonymous
I'm learning C++.
Anonymous
#learn
swagBit
👍
Dexter
Idiot
Anonymous
what is it?
jerry
Visit
Anonymous
I can't get the website open.🤔️
jerry
Now try
Anonymous
not open website
Anonymous
Hey!
Pramodh
/Hii
BinaryByter
It is sad that C and C++ have no built-in operator for rotate
Especially since they come for free in assembler
basicv1
Operating system programs for stimulation in c programming any book......
klimi
Wha